The present invention relates to electronic devices, and more particularly to vertical memory devices, such as eDRAM devices, formed within a silicon-on-insulator (SOI) substrate.
Dynamic Random Access Memory (DRAM) cells are well known. A DRAM cell is essentially a capacitor for storing charge and a pass transistor (also called a pass gate or access transistor) for transferring charge to and from the capacitor. Data (1 bit) stored in the cell is determined by the absence or presence of charge on the storage capacitor. Because cell size affects chip density, and cost, reducing cell area is one of the DRAM designer's primary goals.
One way to accomplish this density goal without sacrificing storage capacitance is to use trench capacitors in the cells. Trench capacitors can be formed by etching deep trenches in a silicon wafer and forming vertically orientated capacitors within each deep trench. Thus, the surface area required for the storage capacitor is dramatically reduced without sacrificing capacitance, and correspondingly, storable charge. Each deep trench may have a depth on the order of 1 μm or greater. In order to further decrease the density of the device, the access transistor can also be positioned in a vertical orientation, as opposed to a planar orientation.
Vertical memory devices are advantageous, in comparison to planar memory configurations, for increased density, performance and lithographic considerations. Vertical memory devices increase density by reducing the cell area of each memory device, therefore allowing for closer positioning of adjacent memory devices. Additionally, each vertically orientated access transistor within each vertical memory device essentially contains a double gate, therefore allowing for increased drive current, in comparison to a single gate utilized in planar access transistors.
There is interest in integrating the excellent drive current and density of vertical memory devices with the superior logic devices that can be formed on silicon-on-insulator (SOI) substrates, to obtain vertical memory embedded dynamic random access memory (eDRAM). SOI substrates reduce parasitic capacitance within the integrated circuit and reduce individual circuit loads, thereby improving circuit and chip performance.
Previous attempts to integrate vertical eDRAM devices with SOI technology have encountered a number of disadvantages. For example, since the trenches, in which vertical eDRAM devices are positioned, typically extend through the buried insulating layer of the SOI substrate, electrical communication must be provided to the memory capacitor through the buried insulating layer. In prior devices, if the vertical device is positioned below the buried insulating layer, the buried insulating layer produces a vertical discontinuity, where electrical communication to the memory device is negatively impacted. Additionally, the thickness of the upper silicon containing layer of the SOI substrate, typically being on the order of about 70 nm to about 100 nm, is too thin to accompany the formation of the entire vertical device without extending into the underlying buried insulating layer.
A vertical memory device is needed that may be integrated with an SOI substrate, where electrical communication from the top surface of the SOI substrate to the access transistor of the memory device is provided without substantially affecting the memory device's physical orientation.